1. Field of the Invention
The present invention relates to image forming apparatuses.
2. Description of the Related Art
Recently, high speed serial buses are developed such as PCIe (Peripheral Component Interconnect Express), and some image forming apparatus are applied a system in which functions are distributed to plural IC (Integrated Circuit) chips which are connected via such a high speed interface.
Such a system which includes plural IC chips connected via a serial bus enables each of the IC chips to be extensible and versatile, and results in small design changes of the IC chips and low cost system development.
FIG. 4 shows a block diagram which indicates an example of an image forming apparatus which includes plural IC chips connected via a serial bus to each other. FIG. 5 shows a block diagram which indicates an example of arbitration priority degree setting for processing circuits on an internal bus in FIG. 4.
In the image forming apparatus shown in FIG. 4, an IC chip 101 and an IC chip 102 are connected via a serial bus to each other, and a memory 103 such as RAM (Random Access Memory) is connected to the IC chip 101.
In the IC chip 101, processing circuits are connected to an internal bus 111, such as a memory controller 112, a serial bus interface 113, an image processing circuit 114, a security module 115, and a serial interface 116.
On the other hand, in the IC chip 102, processing circuits are connected to an internal bus 121, such as a serial bus interface 122, a scan processing circuit 123, a compressing-decompressing circuit 124, a network interface 125, a USB circuit 126, and a parallel interface 127.
In the memory 103, a predetermined memory area is allocated for each of processing circuits such as the image processing circuit 114, the security module 115, and the serial interface 116, a scan processing circuit 123, a compressing-decompressing circuit 124, a network interface 125, a USB circuit 126, and a parallel interface 127. Each of the processing circuits performs data processing using the memory area allocated for itself as a buffer area or the like.
The internal buses 111 and 121 perform arbitration according to arbitration priority degrees of circuits connected to the internal buses 111 and 121. The arbitration priority degree is set as any of plural levels (here, three levels: high, middle, and low).
Among these processing circuits, since real time processing is required for copy job and so forth, arbitration priority degrees of the image processing circuit 114 and the scan processing circuit 123 are set as “high”. Arbitration priority degrees of the serial interface 116, the USB circuit 126, and the parallel interface 127 are set as “low” due to their relatively low speed operation. Arbitration priority degrees of the other processing circuits (the compressing-decompressing circuit 124, the network interface 125, and the security module 115) are set as “middle”.
As shown in FIG. 5, in the respective internal buses 111 and 121 in the IC chips 101 and 102, on the basis of these arbitration priority degrees, unshown arbiters run multiplexers 131 to 133 and 141 to 144. Specifically, in the internal bus 121 of the IC chip 102, the multiplexers 141 to 144 perform arbitration for the processing circuits in the IC chip 102 (i.e. the scan processing circuit 123 to the parallel interface 127), and an access request (either read request or write request) from the processing circuit selected by the arbitration to the memory 103 is transferred to the IC chip 101.
In the internal bus 111 of the IC chip 101, the multiplexers 131 to 133 perform arbitration for the processing circuits in the IC chip 101 (i.e. the serial bus interface 113 to the serial interface 116), and an access request from the processing circuit selected by the arbitration to the memory 103 is provided to the memory controller 112, which performs a memory access (either read or write) specified by the access request.
In the aforementioned system configuration, since the arbitration priority degree of the serial bus interface 113 is set as a constant level (i.e. any of “high”, “middle”, and “low”) in the internal bus 111 of the IC chip 101 to which the memory 103 is connected, arbitration priority degrees in the internal bus 111 of the IC chip 101 can not be set as respective individual levels for the processing circuits in the IC chip 102 (i.e. scan processing circuit 123 to the parallel interface 127).
Therefore, in the aforementioned system configuration, an access request from the processing circuits in the IC chip 102 (i.e. scan processing circuit 123 to the parallel interface 127) to the memory 103 may be not processed adequately according to the original arbitration priority degrees.
If the IC chip 101 and the IC chip 102 are connected via plural channels such as virtual channels of PCIe and the plural channels are assigned to plural arbitration priority degrees, this problem would be solved. However, in this case, the plural channels such as the virtual channels must be available in both of the IC chips 101 and 102, and therefore, large scale circuits would be required for both of the IC chips 101 and 102 (especially, for the serial bus interfaces 113 and 122) and would result in a higher cost of the apparatus.